Senior Verification Engineer

Required Skills
Senior Verification Engineer – 1 Post
Experience: 6-7 years

Job Description
1. Experiance in ASIC verification, preferably baseband/ controller side
2. Experience in Industry standard protocols ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption.
3. Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification.
4. Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage.
5. Experience in Verification methodologies(UVM, OVM and eRM).
6.Mixed language simulation (Verilog-AMS, SystemVerilog).
7. Experience in Mentor, Cadence and Synopsys simulators.
8. Build automated Test bench and regression environments from a scratch. Should be able to write a test plan and generate test cases
9. Regression management and Verification Sign-off based on Functional Verification and Code Coverage.
10. Gate Level Simulation.
11. Generation of Bus Functional Models, Protocol monitors and checkers.
12. Power simulations using CPF/UPF.

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